1. Field of the Invention
The present invention relates to integrated circuit memories, and more particularly to multiple bit per cell read only memory devices.
2. Description of Related Art
The cost of integrated circuit memory devices is closely related to the amount of area on an integrated circuit that is required to store a given amount of data, a parameter often referred to as the density of the device. By saving area on an integrated circuit, a manufacturer is able to make more chips with a given wafer in the fabrication factory. More chips per wafer translates directly to cost savings which can then be passed on to the consumers of the memory devices.
One avenue for increasing the density of memory devices involves storing more than one bit per memory cell. Thus for example, the ability to store two bits per cell allows twice times the data density on an integrated circuit.
Multiple bit per cell technologies have been developed for floating gate memory devices. See U.S. Pat. No.5,163,021 to Mehrotra, et al. However, the floating gate memory approach involves complex charging and discharging of the floating gates, and difficult sensing technology, which increases the complexity and reduces the reliability of the devices.
Another technique for increasing the density of memory devices involves multiple layers of memory cells in a given area on the device. This is typically implemented using thin film techniques in which transistors are stacked on top of one another, creating more than one memory cell per unit area. Typical prior art in this area includes U.S. Pat. No. 5,358,887 invented by Hong. The multi-layer approach reviews special manufacturing steps, and special decoding circuitry which increase cost and reduce reliability.
Accordingly, there is a need for a simpler, low cost technique for implementing multiple bits per cell in a memory device.